In modern communications circuitry, digital phase-locked loops (DPLL's) are used to generate modulated or unmodulated carrier signals by phase locking to a reference signal having a known frequency. DPLL's may employ digital or mixed-signal implementations of such PLL blocks as the loop filter, oscillator, and phase discriminator.
One mixed-signal block commonly found in a DPLL is a time-to-digital converter (TDC), which generates digital representations of continuous time interval durations. A TDC generally quantizes the timing difference between a reference signal and a feedback signal in the DPLL, and may be used, for example, to compute a fractional portion of the number of feedback signal cycles elapsing in one or more reference signal cycles. TDC's typically generate a digital output signal expressed in units of TDC buffer delay, which may then be converted to units of feedback phase by multiplying with a TDC calibration factor.
Inaccuracy in computing the TDC calibration factor, coupled with other factors such as TDC quantization error, may generate phase noise or spurs in the DPLL output signal. It would be desirable to have simple and effective techniques for computing the TDC calibration factor to improve DPLL performance.